In modern mobile communication systems such as High-Speed Downlink Packet Access (HSDPA), High-Speed Uplink Packet Access (HSUPA) and Long Term Evolution (LTE), Hybrid Automatic Repeat Request (HARQ) is used in order to guarantee transmission reliability and increase the channel throughput. HARQ is a powerful combination of Forward Error Correction (FEC), error detection and, if necessary, packet retransmission with Automatic Repeat Request (ARQ) for high channel throughput when feedback is available. In HARQ, when a message is not decoded correctly upon reception, valuable information can be stored temporarily and combined with a subsequent or successive retransmission to correctly decode it. However, in order to implement such scenario, the receiver is required to reserve a certain amount of memory for storing all the erroneous packets or transport blocks (TB) of the message to be combined with the retransmissions of the message. Each TB is formed by a number of independent code blocks (CB). The combination of the TBs is done at soft bit level, which is based on posterior probabilities of the bits that were transmitted. Soft bits are usually stored in the form of log-likelihood ratios (LLRs). Further, in HARQ, when a message is decoded correctly upon reception, the resulting decoded data need be stored by the receiver for use at upper layers of the protocol stack. Due to the ever increasing data rates in the mobile communication systems and the need for supporting multiple HARQ processes in parallel, LLRs storage and decoded data storage are bound to require an increasing amount of memory.
Document (1) U.S. Pat. No. 8,595,605 discloses a method and a wireless communication device for reducing the number of LLRs stored in the local memory. In document (1), where a CB succeeds a cyclic redundancy check (CRC), the decoded CB is stored in a local memory. However, where a CB fails the CRC, the LLRs associated with the CB are only stored in the local memory if a given quality metric is reached. Otherwise, where the given quality metric is not reached, the associated LLRs are stored in an external memory such as a double data rate (DDR) memory attached to the demodulator of the receiver.
It is clear from document (1), that such solution is appropriate where the wireless communication device uses a non-pipelined architecture, in which only one CB is processed at a time. In fact, in the solution of document (1), a CB is sequentially processed by a decoder until the corresponding CRC is obtained so as to determine whether to store the decoded CB in case of CRC success or the associated LLRs in case of CRC failure. This solution cannot work, as such, in pipelined architectures where the HARQ combining operation and the FEC decoding operation are performed concurrently on different stages. For instance, in the case where pipelined architecture is used, the HARQ combining operation and the FEC decoding operation may be performed on different CBs at the same time. Hence, for instance, where FEC decoding operation is performed on a given CB, there is performed at the same time HARQ combining operation on the subsequent CB. Therefore, in case of CRC failure at the end of the FEC decoding operation, it is too late to retrieve the associated LLRs for storage, because the HARQ combining operation may have overwritten them with the LLRs associated with the subsequent CB being currently processed.
Accordingly, the prior art solutions described in document (1) suffers from a high amount of memory and data traffic needed at the receiver level for both foregoing type of storages, in a pipelined decoder.